C-PHY v3.1 Verification IP 

Truechip's C-PHY Verification IP provides an effective & efficient way to verify the components interfacing with C-PHY interface of an IP or SoC. Truechip's C-PHY VIP is fully compliant with MIPI C-PHY Specification version 3.1. The VIP is light weight with easy plug-and- play interface so that there is no hit on the design cycle time.

Key Benefits

• Available in native System Verilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and coverage points with connectivity examples for all the components
• Consistency of interface, installation, operation, and documentation across all our VIPs
• Provide complete solutions and easy integration in IP and SoC environment

Features

• Compliant to MIPI C-PHY Specification version 3.1 with PPI interface, backward compatible with v3.0, v2.1, v2.0, v1.2, v1.1 and v1.0.
• Supports all configuration of a data lane module as specified in Figure 9 of C-PHY specification version 3.1 for Data Lane Module (PFAA & SFAA, PFAE & SFAE, PFEA & SFEA, PFAN & SFAN, PFEE & SFEE, PFEN & SFEN).
• Supports ULPS, Triggers and LPDT in low power escape mode.
• Bi-directional Data lane turnaround is supported for escape mode
• Configurable number of Data Lanes.
• Supports High-Speed mode and Low Power Escape and Control modes.
• Supports continuous and non-continuous clock behaviour.
• Supports 18-Wirestate mode encoding scheme with 32-bit to 9-symbol (32b9s) Mapper and 9-symbol to 32-bit Demapper, in addition to 6-Wirestate mode with 16-bit to 7-symbol Mapper & 7-symbol to 16-bit Demapper.
• Supports symbol encoding and decoding.
• Supports dynamically configurable modes.
• Strong Protocol Monitor with real time exhaustive programmable checks.
• Supports Dynamic as well as Static Error Injection scenarios.
• On the fly protocol checking using assertions.
• Built in Coverage analysis.
• Provides a comprehensive user API (callbacks) in Master & slave.
• Graphical analyser to show transactions for easy debugging.

Deliverables

• MIPI C-PHY Master/Slave BFM/Agent
• MIPI C-PHY Monitor
• MIPI C-PHY Scoreboard
• Testbench Configurations
• Test Suite (Available in Source code)
  • Basic and Directed Protocol Tests
  • Random Tests
  • Error Scenario Tests
  • Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Notes